Cmos semiconductor devices having dual work function metal gate stacks

ABSTRACT

CMOS semiconductor devices having dual work function metal gate structures that are formed using fabrication techniques that enable independent work function control for PMOS and NMOS device and which significantly reduce or otherwise eliminate impact on gate dielectric reliability.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Korean Patent Application No. 2006-0009367, filed on Jan. 31, 2006, which is incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

The present invention relates, generally, to CMOS semiconductor devices having dual work function metal gate structures, as well as methods for fabricating dual metal gate stack structures providing separate gate work function control for PMOS and NMOS transistors.

BACKGROUND

In general, complementary metal oxide silicon (CMOS) semiconductor integrated circuits are formed with pairs of p-channel MOS (PMOS) and n-channel MOS (NMOS) transistors that work cooperatively with each other. CMOS semiconductor devices have higher operation efficiency and speed as compared to semiconductor devices formed using only PMOS transistors. Moreover, CMOS technology has good scaling characteristics, which has allowed development of semiconductor integrated circuit devices with increasingly higher integration densities. For these and other reasons, CMOS technology is commonly used to fabricate semiconductor devices for highly-integrated and high-performance applications. As CMOS technology downscales to nanometer levels and beyond, however, supply voltages and MOS transistor threshold voltages must also be continually scaled down to maintain high-performance and high-reliability. The aggressive downscaling of CMOS transistors has posed technological challenges with respect to development of gate stack structures having well-controlled and reproducible work functions/threshold voltages.

Conventional CMOS fabrication techniques have employed a polycrystalline silicon (poly-Si) gate electrode process technology. FIG. 1A illustrates a conventional CMOS gate structure for MOS devices. FIG. 1A illustrates, a gate structure (10) formed on a semiconductor substrate (11). The gate structure (10) comprises a polysilicon (poly-si) gate electrode (10 a) and a gate dielectric layer (10 b) interposed between the gate electrode (10 a) and the semiconductor substrate (11). In conventional gate stack designs, the gate dielectric layer (10 b) is formed of a thermally grown silicon oxide, for example. The conventional gate structure (10) is insufficient to meet performance requirements in nanoscale CMOS technology. For example, at nanoscale design rules, the contact area of the poly-si gate electrode (10 a) is significantly decreased, thereby requiring the thickness of the gate dielectric layer (10 b), such as silicon oxide, to be decreased so as to maintain the gate capacitance that is required for proper device performance.

When a poly-si gate stack structure (such as depicted in FIG. 1A) is formed with ultra-thin gate dielectric layer, device performance can be significantly degraded due to poly-si gate depletion (i.e., PDE (poly-gate depletion) effect), high gate resistance (smaller poly gate), increased gate dielectric tunneling leakage current, and other well-known problems. In particular, with poly-si gate depletion, a thin depletion layer is formed between the polysilicon gate electrode (10 a) and the thin gate dielectric layer (10 b), which increases the equivalent gate oxide thickness, resulting in a reduction of the total gate capacitance.

To overcome problems associated with ultra-thin gate dielectric layers with poly-si gate stacks, high-K gate dielectric materials were considered for use as gate dielectric layers for poly-si gate stacks, which allowed for thicker gate dielectric layers under the same effective oxide thickness. This approach is effective to eliminate gate dielectric tunneling leakage, but there are compatibility problems when interfacing high-K dielectric materials with poly-Si gate electrodes. For examples in the absence of a diffusion barrier, oxidants in the high-k dielectric layer can easily diffuse into the poly-Si gate electrode forming a silicon oxide layer at the interface, resulting in decreased gate capacitance. Moreover, gate stack structures formed with high-k dielectrics layers interfaced with poly-Si gate electrodes do not overcome the PDE effect.

Advanced gate stack solutions for nanoscale CMOS devices have employed high-K gate dielectric layers and metal gate electrodes to eliminate the problems of gate depletion, gate dielectric tunneling leakage and limitations in capacitance equivalent thickness downscaling. FIG. 1B illustrates a conventional CMOS gate structure (20) formed on a semiconductor substrate (21). The gate structure (20) comprises a polysilicon gate electrode (20 a), a gate dielectric layer (20 b), and a metal gate layer (20 c) interposed between the poly-si electrode (20 a) and the gate dielectric layer (20 b). In some conventional designs, the same metallic material is used to form the metal gate layer (20 c) for both the PMOS and NMOS gate stacks. Although the metal gate layer (20 c) is effective to prevent gate depletion effects and dopant penetration from the poly-si gate into the gate dielectric layer, a drawback to this approach is that the threshold voltages of the PMOS and NMOS transistors are determined primarily by the work function of the inserted metal gate layer (20 c).

Ideally, metal gates with work functions corresponding to the conduction and valence band edges of Si are optimal for bulk-Si NMOS and PMOS transistors, respectively. However, single work function metal gate technologies must balance between the optimal work functions for the NMOS and PMOS transistors. For example, the metal gate layer for the NMOS and PMOS transistors may be formed of a metal having a Fermi level between energy levels of conduction and valence bands of the semiconductor layer. A drawback to this approach is that the threshold voltages Vth of the transistors are increased to levels that cannot be effectively reduced using channel counter doping techniques. Thus, single work function metal gate CMOS technologies may be ineffective to meet the threshold voltage scaling requirements that are needed to achieve low-power consumption and high speed device performance.

Accordingly, dual work function metal gate CMOS technologies have been proposed in which the gate metal layers of the NMOS and PMOS gate stacks are formed from different metals having Fermi levels or work functions that correspond to the conduction and valance band edges of Si. For example, the metal layer in the NMOS gate stack can be formed of a metal having a Fermi level similar to the energy level of the conduction band of an n+-doped silicon layer, and the metal layer in the PMOS gate stack can be formed of a metal having a Fermi level similar to the energy level of the valence band of a p+-doped silicon layer.

The development of dual work function metal gate techniques have posed technological challenges with regard to selection of metals having material properties which allow for separate control of the NMOS and PMOS gate work functions and which are suitable for integration with CMOS process technologies. By way of specific example, with dual metal gate fabrication processes, consideration should be given to the material characteristics of the gate metal/dielectric materials that are used to form the gate stacks so as to enable tight control and reproducibility of gate work functions. Moreover, consideration should be given the type of thin film processing techniques that are employed for device fabrication so as to prevent damage to the gate dielectric layer, which would degrade electrical performance or otherwise reduce the reliability and expected lifetime of the gate stack structure.

For example, a conventional dual metal gate stack fabrication process includes forming a gate dielectric layer on a semiconductor substrate and forming a first metal layer on the gate dielectric layer, wherein the first metal layer is selected to set the work function for, e.g., the NMOS gate. Thereafter, the first metal layer is patterned to remove the portion of the first metal layer in the PMOS region. A second metal layer is then formed over the exposed gate dielectric layer in the PMOS region, wherein the second metal layer is selected to set the work function for, e.g., the PMOS gate. The second metal layer is then etched to remove the portion of the second metal layer in the NMOS region that is formed over the first metal layers. In this process, when the first metal layer is etched, the gate dielectric layer in the PMOS active region is used as an etch stop. Consequently, the gate dielectric layer in the PMOS stack can be damaged by the processing steps.

In another conventional method, after the first metal layer is patterned (metal etch process), the gate dielectric layer is removed and a new gate dielectric layer is formed (i.e., removing potentially damaged gate dielectric layer). This approach is effective to improve the quality of the gate dielectric layer, but can result in damage to the first metal layer during fabrication of the new gate dielectric layer. For instance, the first metal layer can be oxidized when an oxidation process is employed to thermally grow an oxide layer for the gate dielectric. Moreover, when the new dielectric layer is formed using thin film deposition techniques (e.g., PVD), the exposed region of the active silicon and gate dielectric layer can be damaged during the plasma process.

SUMMARY OF THE INVENTION

In general, exemplary embodiments of the present invention include CMOS semiconductor devices having dual work function metal gate structures, as well as methods for fabricating dual metal gate stack structures providing dual gate work function control for PMOS and NMOS transistors. Exemplary fabrication techniques according to the invention in consideration of material characteristics and thin film processing techniques to significantly reduce or otherwise eliminate impact on gate dielectric reliability,

In one exemplary embodiment of the invention a semiconductor device includes a semiconductor substrate having a dual-gate CMOS device formed on a front-side of the semiconductor substrate. The dual-gate CMOS device includes a PMOS device and an NMOS device. The PMOS device has a first gate stack formed of a gate insulator layer formed on the semiconductor substrate, a first conductive layer formed on the gate insulator layer, a second conductive layer formed on the first conductive layer, and a third conductive layer formed on the second conductive layer. The NMOS device has a second gate stack including a gate insulator layer formed on the semiconductor substrate, a first conductive layer formed on the gate insulator layer, and a second conductive layer formed on the first conductive layer.

In one exemplary embodiment, the second conductive layers of the first and second gate stacks are formed from different conductive materials. In another embodiment, the first conductive layers of the first and second gate stacks are formed of a same conductive material having substantially the same thickness. For example, the first conductive layers of the first and second gate stack are formed of TaN or TiN. The thickness and the conductive material of the first conductive layers of the first and second gate stacks is selected to modulate a work function of the NMOS device. The thickness and a conductive material of the second conductive layer of the first gate stack is selected to modulate a work function of the PMOS device.

In one exemplary embodiment, the first, second and third conductive layers of the first gate stack are formed of different conductive materials. The first conductive layer is preferably formed of a material that has an etch selectivity that is larger than an etch selectivity of the different materials that form the second and third conductive layers of the first gate stack with regard to an HF etching solution, for example. This enables removal of the portions of the second and third layers in the region of the second gate stack during a fabrication process. For example, the first, second and third conductive layers of the first gate stack of the PMOS device are formed of TaN, AlN and HfN, respectively.

In other exemplary embodiments, the gate insulating layers of the first and second gate stacks is formed of a dielectric material having a dielectric constant in a range of about 8 and greater. An interfacial layer may be interposed between the gate insulating layers and the semiconductor substrate to prevent reaction between the high-k dielectric material and the silicon substrate. The gate insulating layers of the first and second gate stacks may be formed of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, yttrium oxide, or aluminum oxide.

These and other exemplary embodiments, aspects, objects, features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-sectional schematic view of a conventional gate stack structure of a MOSFET transistor.

FIG. 1B is a cross-sectional schematic view of another conventional gate stack structure of a MOSFET transistor.

FIG. 2 is a cross-sectional schematic view of a CMOS transistor pair having dual work function metal gate structures in accordance with an exemplary embodiment of the invention.

FIGS. 3A-3E are cross-sectional schematic views of the CMOS transistor pair of FIG. 2 at various stages of a CMOS fabrication process according to an exemplary embodiment of the invention.

FIGS. 4A and 4B are exemplary illustration of experimental data of threshold voltage as a function of thickness of a gate metal layer for NMOS and PMOS devices.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments of the invention will now be described more fully with reference to the accompanying drawings in which it is to be understood that the thickness and dimensions of the layers and regions are exaggerated for clarity. It is to be further understood that when a layer is described as being “on” or “over” another layer or substrate, such layer may be directly on the other layer or substrate, or intervening layers may also be present. Moreover, similar reference numerals used throughout the drawings denote elements having the same or similar functions.

FIG. 2 is a cross-sectional schematic view of a CMOS transistor pair having dual work function metal gate stack structures according to an exemplary embodiment of the invention. In particular, FIG. 2 illustrates a semiconductor device (100) comprising a semiconductor substrate (101) having an NMOS transistor region (101 a) and a PMOS transistor region (101 b). The NMOS transistor region (101 a) includes an NMOS transistor comprising n-doped drain/source diffusion regions (170) formed in a p-doped device well, and a gate stack structure (140) comprising a gate dielectric layer (103 a), and a gate electrode (141). The gate electrode (141) comprises a first conductive layer (111 a) formed on the gate dielectric layer (103 a) and a second conductive layer (120 a) formed on the first conductive layer (111 a). An optional interfacial layer (102 a) is interposed between the gate dielectric layer (103 a) and the substrate.

The PMOS transistor region (101 b) includes a PMOS transistor comprising p-doped drain/source diffusion regions (171) formed in an n-doped device well, and a gate stack structure (150) comprising a gate dielectric layer (103 b) and a gate electrode (151). The gate electrode (151) comprises a first conductive layer (111 b), a second conductive layer (113 b), a third conductive layer (115 b) and a fourth conductive layer (120 b) formed cover the gate dielectric layer (103 b). The gate structures (140 and (150) of respective NMOS and PMOS transistors have respective insulating spacers (160 a, 160 b) formed on the sidewall surfaces and insulating caps (130 a, 130 b) formed on the top surfaces of respective gate stacks (140, 150).

In one exemplary embodiment of the CMOS transistor of FIG. 2, the NMOS gate structure (140) comprises a metal-inserted gate layer comprising the first conductive layer (111 a) (single metal layer) interposed between the gate dielectric layer (103 a) and a polysilicon layer (120 a). An optional interfacial layer (102 b) is interposed between the gate dielectric layer (103 b) and the substrate. The PMOS gate structure (150) comprises a metal-inserted gate layer comprising a stack of three conductive metal layers (111 b/113 b/115 b), interposed between the gate dielectric layer (103 b) and a polysilicon layer (120 b). The metal layer (111 a) is formed of a first metallic material and thickness so that the NMOS gate has a work function similar to the work function of the p-doped silicon and to control the threshold voltage of the NMOS transistor. The metal-inserted layer of the PMOS gate stack (150) is formed of three metal layers (111 b/113 b/115 b) with materials and thickness selected to provide an effective work function of the PMOS is the same or similar to the work function of the n-doped silicon and control the threshold voltage of the PMOS device.

Various dielectric/metal material systems have been considered for constructing the gate stacks (140) and (150) to achieve well controlled dual gate work functions. For example, the effect of TaN as an inserted metal on the threshold voltage characteristics of CMOS transistors has been considered. In general, the threshold voltage of an NMOS transistor significantly increases as a function of increase in thickness of TaN gate layer, whereas the threshold voltage of a PMOS transistor slightly decreases and levels off as the thickness of the TaN gate layer increases. For instance, the effect of the threshold voltages of the NMOS and PMOS transistors with TaN as an inserted metal and HfO2 as a gate dielectric layer is illustrated in FIGS. 4A and 4B, respectively. As illustrated, it can be considered that threshold voltages of about 0.55 and −0.6 for respective NMOS and PMOS transistors can generally be achieved using a thin layer of TaN (10 angstroms) for the NMOS device and a thick TaN (40 angstroms) for the PMOS device.

It has been further determined that a material such as AlN a metal gate layer can further decrease the threshold voltage of a PMOS transistor. For instance, for a PMOS transistors with TaN as an inserted metal (of thickness of 40 angstroms) and HfO2 as a gate dielectric layer as illustrated in FIG. 4B, a further reduction in threshold voltage of the PMOS device can be achieved by interposing a thin layer (e.g., 10 angstroms) of ALN (or a material having similar characteristic) between two layers of TaN of thickness of 20 angstroms (or metal layers having similar characteristics of TaN).

In one exemplary embodiment, the first conductive layer (111) is formed to provide a work function from about 4.0 to about 4.4 eV for the NMOS gate electrode. The first conductive layer (111) can be formed of metals such as W, MO, Ti, Ta, Al, Hf, or Zr, or nitrides of such metals, or Al or Si doped nitride of such metals. In particular, the first conductive layer (111 a) can be formed of a metallic nitride material such as TiN or TaN having a suitable work function to set the threshold voltage of the NMOS device.

Furthermore, in one exemplary embodiment of the invention, the stack of conductive layers (111 b/113 b/115 b) are formed of conductive materials and thicknesses that are selected to determine an effective work function of the PMOS gate electrode from about 4.7 to about 5.1 eV for the PMOS gate electrode. In particular, given that the first conductive layer (111 b) material and thickness is selected to determine the work function of the NMOS gate electrode (the first conductive layer (111 a) of gate stack (140) has a suitable work function similar to that of n-type silicon), the second conductive layer (113 b) is provided to modulate the work function of the PMOS gate (150) using a metal having a suitable work function so as to effectively increase the work function of the PMOS gate electrode.

The second conductive layer (113 b) can be formed of a metal such as Al, La Y, or an oxide or nitride of such metals. The third conductive layer (115 b) is formed of a conductive material and thicknesses that provides further reduction of the threshold voltage of the PMOS transistor. The third conductive layer (115 b) may be formed of a material that is the same as or similar to the material of the first conductive layer (111 b). For example, the third conductive layer may be formed of W, MO, Ti, Ta, Al, Hf, or Zr, or nitrides of such metals, or Al or Si doped nitride of such metals.

In one exemplary embodiment of the invention, dual work function control can be obtained for CMOS transistor where the NMOS gate stack (140) is formed of a high-k dielectric layer/thin TaN metal layer/poly-Si gate electrode and the PMOS gate stack (150) is formed of high-k dielectric layer/thin TaN metal layer/thin AlN layer/thin HfN layer/poly-Si gate electrode. In this exemplary embodiment, the first, second and third conductive layers (111 b/113 b/115 b) of PMOS gate are formed of different conductive materials TaN (or TiN), AlN (or AlO) and HfN (or TaN), respectively. The TaN and HfN layers have an effective thickness providing a relatively stable threshold voltage for the PMOS device, and the intervening AlN layer provides work function modulation so as to further controllably reduce the threshold voltage of the PMOS device.

In other exemplary embodiments of the invention, a CMOS transistor can be constructed having an NMOS gate structure with a metal-inserted gate layer comprising a stack of three conductive metal layers, interposed between a gate dielectric layer and a polysilicon layer. The metal-inserted layer of the NMOS gate stack can be formed with three metal layers with materials and thickness selected to provide an effective work function of the NMOS which is the same or similar to the work function of the p-doped silicon and control the threshold voltage of the PMOS device. Moreover, the PMOS gate structure may comprise a metal-inserted gate layer comprising the first conductive layer (single metal layer) interposed between the gate dielectric layer and the polysilicon layer, where the metal layer is preferably formed of a first metallic material and thickness so that the PMOS gate has a work function similar to the work function of the n-doped silicon and to control the threshold voltage of the PMOS transistor.

It is to be understood that the various materials used to form the gate stacks can vary depending on the application and desired work function control and that the above stack frameworks are merely illustrative. Moreover, the materials that are used to form the gate layers may be varied depending on the issues of compatibility (e.g., interactions at the interface of gate layers) and the fabrication processes that are employed.

FIGS. 3A˜3E are schematic cross-sectional views illustrating a method of fabricating a dual work function metal gate CMOS semiconductor device according to an exemplary embodiment of the invention. FIG. 3A illustrates initial process steps starting with a bulk semiconductor substrate (101) and forming NMOS and PMOS transistor regions (101 a) and (101 b) comprising respective p-doped and n-doped device wells (i.e., active regions) in a surface of the silicon substrate (101) using known techniques. For instance, an isolation region can be formed to define the NMOS and PMOS active regions (101 a) and (101 b) using shallow trench isolation (STI) methods or local oxidation of silicon (LOCOS) and doping the active regions using ion implantation techniques to form the desired n-doped and p-doped device wells.

Thereafter, an optional interfacial layer (112) can be formed over the substrate (101) and a gate dielectric layer (103) is formed on the interfacial layer (102). In one exemplary embodiment, the gate dielectric layer (103) can be silicon oxide formed by a thermal oxidation process. In another embodiment, the gate dielectric layer (103) can be a silicon nitride layer formed by a heat treatment process in a nitrogen atmosphere. When the gate dielectric layer (103) is formed of a silicon oxide or silicon nitride, the interfacial layer (102) is not needed. The gate dielectric layer (103) is preferably formed to have a thickness in a range of about 10 angstroms to about 60 angstroms, when formed of a silicon oxide or silicon nitride.

The interfacial layer (102) is preferably formed when the gate dielectric layer (103) is formed of a high-k dielectric material so as to prevent reaction between the gate dielectric material and the silicon substrate (101). The interfacial layer (102) can be formed by a cleaning process including ozone gas and ozonized liquid to form a thin interfacial layer of about less than 1.5 nm in thickness.

The gate dielectric layer (103) can be a high-k dielectric material having a relative dielectric constant that is greater than that of silicon oxide. For example, the high-k dielectric layer (103) may be formed of a material having a dielectric constant of 8 or higher such as hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, GdO, yttrium oxide, or aluminum oxide, a silicate, or any combination thereof. The high-k gate dielectric layer (103) can be formed using well-known deposition techniques such as CVD, PVD or ALD.

A post deposition appeal (PDA) process can be performed for densification of the high-k dielectric layer (103) in an environment with N2, NO, N2O, O2 or HNH3 gases and a temperature ranging from about 750° C. to about 1050° C. including N2, NO, N2O, O2 or HNH3 gases. The gate dielectric layer (103) can be formed of a dielectric material having a dielectric constant in a range of about 8 and greater. The thickness of the gate dielectric layer (103) will vary depending on the relative dielectric constant of the high-k dielectric material used to form the gate dielectric layer (103). For example, the thickness of the high-k dielectric layer can be in a range of about 10 angstroms to about 200 angstroms.

Next, referring to FIG. 3B, a series of deposition processes are performed to form a first conductive layer (111) on the gate dielectric layer (103), a second conductive layer (113) on the first conductive layer (111) and to form a third conductive layer (115) on the second conductive layer (113). The conductive layers (111), (113 and (115) are formed of metallic materials and thicknesses that are selected to define dual work functions for the NMOS and PMOS gate electrodes, while enabling formation of the gate stacks using well-controlled processing steps so as to eliminate or significantly mitigate damage to the gate stack layers during fabrication.

In one exemplary embodiment of the invention, the first conductive layer (111) is formed of a conductive material and thickness that is selected to determine a work function of the NMOS gate electrode (which determines the threshold voltage of the NMOS transistor). In one exemplary embodiment, the first conductive layer (111) is formed to provide a work function from about 4.0 to about 4.4 eV for the NMOS gate electrode. The first conductive layer (111) can be formed of metals such as W, MO, Ti, Ta, Al, Hf, or Zr, or nitrides of such metals, or Al or Si doped nitride of such metals. In particular, the first conductive layer (111) can be formed of a metallic nitride material such as TiN or TaN, which are preferable to provide etch selectively with respect to the second and third conductive layers (113) and (115) for a subsequent etching process as described below. The first conductive layer (111) is preferably formed having a thickness in a range of about 5 angstroms to about 60 angstroms.

Furthermore, in one exemplary embodiment of the invention, the stack of conductive layers (111/113/115) are formed of conductive materials and thicknesses that are selected to determine an effective work function of the PMOS gate electrode (which determines the threshold voltage of the PMOS transistor). In one exemplary embodiment, the stack of conductive layers (111/113/115) is formed to provide an effective work function from about 4.7 to about 5.1 eV for the PMOS gate electrode. In particular, given that the first conductive layer (111) is selected to determine the work function of the NMOS gate electrode (the first conductive layer (111) has a suitable work function similar to that of n-type silicon), the second conductive layer (113) is provided to modulate the work function of the PMOS gate using a metal having a suitable work function so as to effectively increase the work function of the PMOS gate electrode to provide a work function similar to that of p-type silicon. As noted above, the second conductive layer (113) can be formed of a silicon oxide, silicon nitride or a metal such as Al, La Y, or an oxide or nitride of such metals. The second conductive layer (113) is preferably formed having a thickness in a range of about 1 angstroms to about 30 angstroms, depending on the material that is used.

Furthermore, in one exemplary embodiment of the invention, the third conductive layer (115) is formed of a conductive material and thicknesses that provides further reduction of the threshold voltage of the PMOS transistor. The third conductive layer (115) may be formed of a material that is the same as or similar to the material of the first conductive layer (111). For example, the third conductive layer may be formed of W, MO, Ti, Ta, Al, Hf, or Zr, or nitrides of such metals, or Al or Si doped nitride of such metals.

Referring to FIG. 3C, a photo-resist pattern (117) is formed on the third conductive layer (115) to expose the NMOS region (101 a) and cover the PMOS region (101 b). The third and second conductive layers (115) and (113) are then sequentially etched and removed from the NMOS region (101 a). The etch process may be performed using etching techniques that prevent damage to the metal and gate dielectric layers. For instance, in one exemplary embodiment of the invention, the material of the first conductive layer (111) is selected to have an etch selectively that is greater than that of the materials forming the second and third conductive layers (113) and (115).

By way of specific example, the etch process may be performed using a wet etch process using an HF solution, where the etch selectively of the first conductive layer (111) for the HF solution is greater than that of the second and third conductive layers (113 and 115). In this regard, the second and third conductive layers (13) and (115) can be easily removed using the HF wet etch using the first conductive layer (111) as an etch stop while avoiding etching damage to the first conductive layer (111), and avoiding damage to the NMOS gate dielectric layer (103 a) (as it is not exposed during the etch step).

For instance, a gate layer formed of TaN or TiN can not be dissolved in an 200:1 HF solution, but gate layers formed of materials such as HfN and AlN are easily dissolvable in such HF solution. In this regard, assuming that the first conductive layer (111) is formed of TaN, the second conductive layer (113) is formed of AlN, and the third conductive layer (115) is formed of HfN, the portion of the second and third conductive layers of AlN and HfN in the NMOS region (101 a) can be readily etched away (high etch rate) to expose the first conductive layer of TaN (111), without etching or otherwise damaging the first conductive layer (111).

Next, referring to FIG. 3D, the photoresist pattern (117) is removed using known techniques. For instance, the photoresist pattern (117) can be removed using an ashing process in an O2 ambient, or in an H2, N2, NH3 or He ambient. In a non-O2 ambient, a plasma may be generated and fluorinated gases such as CF4 may be added to increase the removal rate of the photoresist pattern (117). A non-O2 ashing process is advantageous to avoid degradation or damage to the exposed portions of the gate dielectric layer (103).

Next, another layer of conductive material (120) is formed over the substrate (101). For example, the layer of conductive material (120) may be polysilicon, a metal oxide, a metal nitride, a silicide or any suitable metal. The conducive material (120) is used to form the third conductive layer (120 a) of the NMOS gate stack (140) and the fourth conductive layer (120 b) of the PMOS gate stack (150) (FIG. 2). The layer of conductive material (120) may be deposited using known techniques and subsequently planarized using known techniques, depending on the material used.

Next, a hard mask layer (130) is deposited and patterned to form a mask pattern (130 a, 130 b) using known techniques, which define the gate stack areas in the NMOS and PMOS regions (101 a, 101 b), respectively. For instance, the hard mask layer (130) may be formed of silicon nitride or other suitable insulating materials using CVD (chemical vapor deposition) or ALD (atomic layer deposition), for example, and subsequently patterned using known photolithographic methods. Thereafter, an anisotropic etch process is performed using the mask pattern (130 a, 130 b) as an etch mask to etch down to the surface of the substrate (101) and form the gate stack structures (140) and (150), such as depicted in FIG. 3D. Thereafter, well-known, process steps can be used to form side wall spacers (160 a, 160 b) for the gate stacks (140) and (150) and drain-source diffusion regions (170, 171) for the NMOS and PMOS transistors.

Although exemplary embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to the exemplary embodiments described herein, and that various other changes and modifications may be readily envisioned by one of ordinary skill in the art without departing form the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims. 

1. A semiconductor device, comprising: a semiconductor substrate having a dual-gate CMOS device formed on the semiconductor substrate, the dual-gate CMOS device comprising a PMOS device and an NMOS device, wherein the PMOS device has a first gate stack comprising: a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a second conductive layer formed on the first conductive layer; and a third conductive layer formed on the second conductive layer, wherein the NMOS device has a second gate stack comprising: a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; and a second conductive layer formed on the first conductive layer, and wherein the second conductive layers of the first and second gate stacks are formed from different conductive materials.
 2. The semiconductor device of claim 1, wherein the first conductive layers of the first and second gate stacks are formed of a same conductive material and have a substantially same thickness.
 3. The semiconductor device of claim 2, wherein the first conductive layers of the first and second gate stacks are formed of a metallic nitride.
 4. The semiconductor device of claim 3, wherein the first conductive layers of the first and second gate stack are formed of TaN or TiN.
 5. The semiconductor device of claim 2, wherein the thickness and the conductive material of the first conductive layers of the first and second gate stacks is selected to modulate a work function of the NMOS device.
 6. The semiconductor device of claim 2, wherein a thickness and a conductive material of the second conductive layer of the first gate stack is selected to modulate a function of the PMOS device.
 7. The semiconductor device of claim 1, wherein the first and second conductive layers of the first gate stack are formed of different metallic nitride materials.
 8. The semiconductor device of claim 7, wherein the metallic nitride materials include TiN, TaN, or AlN.
 9. The semiconductor device of claim 1, wherein the first, second and third conductive layers of the first gate stack are formed of different conductive materials.
 10. The semiconductor device of claim 9, wherein the first conductive layer is formed of a material that has an etch selectivity that is larger than an etch selectivity of the different materials that form the second and third conductive layers of the first gate stack with regard to an HF etching solution.
 11. The semiconductor device of claim 10, wherein the first, second and third conductive layers of the first gate stack of the PMOS device are formed of TaN, AlN and HfN, respectively.
 12. The semiconductor device of claim 10, wherein the first, second and third conductive layers of the first gate stack of the PMOS device are formed of HfN, AlN and TaN, respectively.
 13. The semiconductor device of claim 1, wherein the gate insulating layers of the first and second gate stacks is formed of a dielectric material having a dielectric constant in a range of about 8 and greater.
 14. The semiconductor of claim 13, further comprising an interfacial layer interposed between the gate insulating layers and the semiconductor substrate.
 15. The semiconductor device of claim 13, wherein the gate insulating layers of the first and second gate stacks are formed of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, yttrium oxide, or aluminum oxide.
 16. The semiconductor device of claim 1, wherein the first gate stack of the PMOS device further comprises a fourth conductive layer formed on the third conductive layer.
 17. The semiconductor device of claim 16, wherein the second conductive layer of the second gate stack and the fourth conductive layer of the first gate stack are formed of a same conductive material.
 18. The semiconductor device of claim 16, wherein the second conductive layer of the second gate stack and the fourth conductive layer of the first gate stack are formed of a polysilicon material.
 19. The semiconductor device of claim 1, wherein the thickness of first conductive layers of the first and second gate stacks is in a range of about 5 angstroms to about 60 angstroms.
 20. A semiconductor device, comprising: a semiconductor substrate having a dual-gate CMOS device formed on a front-side of the semiconductor substrate, the dual-gate CMOS device comprising a PMOS device having a first MIPS gate stack, and an NMOS device having a second MIPS gate stack, wherein the first and second MIPS gate stacks each comprise: a gate insulating layer formed on the semiconductor substrate; a polysilicon electrode; and a metal inserted layer interposed between the gate insulating layer and the polysilicon electrode, wherein the metal inserted layer of the first MIPS gate stack comprises a stack of at least first, second and third metallic layers; and wherein the metal inserted layer of the second MIPS gate stack comprises at least a first metallic layer.
 21. The semiconductor device of claim 20, wherein the first metallic layers of the first and second MIPS gate stacks are formed of a same metallic material and have a same thickness in a range of about 5 angstroms to about 60 angstroms.
 22. The semiconductor device of claim 21, wherein the first metallic layers of the first and second MIPS gate stacks are formed of a metallic nitride
 23. The semiconductor device of claim 22, wherein the thickness and the metallic nitride material of the first conductive layers of the first and second MIPS gate stacks is selected to modulate a work function of the NMOS device.
 24. The semiconductor device of claim 21, wherein a thickness and a conductive material of the second metallic layer of the first MIPS gate stack is selected to modulate a work function of the PMOS device.
 25. The semiconductor device of claim 20, wherein the first, second and third metallic layers of the first MIPS gate stack are formed of different conductive materials.
 26. The semiconductor device of claim 25, wherein the first, second and third metallic layers of the first MIPS gate stack are formed of TaN, AlN and HfN, respectively.
 27. The semiconductor device of claim 25, wherein the first, second and third metallic layers of the first MIPS gate stack are formed of HfN, AlN and TaN, respectively.
 28. The semiconductor device of claim 20, wherein the gate ins insulating layers of the first and second MIPS stacks are formed of a dielectric material having a dielectric constant in a range of about 8 and greater.
 29. The semiconductor of claim 20, further comprising an interfacial layer interposed between the gate insulating layers and the semiconductor substrate.
 30. A method for fabricating a semiconductor device having a dual-gate CMOS device, the method comprising: defining an active region of a CMOS device on a semiconductor substrate, the active region comprising an NMOS device region and a PMOS device region; forming a gate insulating layer on the semiconductor substrate; forming a first conductive layer on the gate insulating layer; forming a second conductive layer on the first conductive layer; forming third conductive layer on the second conductive layer; performing an etch process to etch the third and second conductive layers down to the first conductive layer in the NMOS device region; and forming a first gate structure in the PMOS region and second gate structure in the NMOS region, wherein the first gate structure is stacked structure formed from the gate insulating layer and first and second conductive layers, and wherein the second gate structure is a stacked structure formed from the gate insulating layer and the first conductive layer.
 31. The method of claim 30, wherein the third and second conductive layers are etched using an etch process wherein an etch selectivity of the first conductive layer is larger than an etch selectivity of the second and third conductive layers such that the first conductive layer serves as an etch stop.
 32. The method of claim 31, wherein the etch process is a wet etch process using an HF solution.
 33. The method of claim 32, wherein the first conductive layer is formed of TaN, wherein the second conductive layer is formed of AlN and wherein the third conductive layer is formed of HfN.
 34. The method of claim 30, wherein forming the first and second gate structures comprises: forming a fourth conductive layer over the NMOS and PMOS regions; forming an etch mask on the fourth conductive layer, wherein the etch mask defines a gate pattern for the first and second gate structures; etching the fourth conductive layer downs to the substrate to form the first and second gate structures.
 35. The method of claim 34, wherein the fourth conductive layer comprises polysilicon.
 36. The method of claim 34, wherein the fourth conductive layer comprises a metallic material.
 37. The method of claim 36, wherein the fourth conductive layer comprises a metal silicide or nitride material.
 38. The method of claim 30, wherein forming the gate insulating layer comprises: forming an interfacial layer on the semiconductor substrate; and forming a layer of gate dielectric material over the interfacial layer.
 39. The method of claim 38, wherein the gate dielectric material has a dielectric constant in a range of about 8 and greater.
 40. The method of claim 39, wherein the gate dielectric material gate insulating layers of the first and second gate stacks are formed of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, yttrium oxide, or aluminum oxide. 